dmy@lab
|
7e5c6c71a1
|
添加直接给出DG有功、无功的函数
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-03-10 20:39:57 +08:00 |
dmy@lab
|
5825d156f6
|
把短阻抗改为0.0001
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-03-10 20:12:24 +08:00 |
dmy@lab
|
46f890b77b
|
修复了合并线路后没用重新计算阻抗的问题
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-03-09 16:26:47 +08:00 |
dmy@lab
|
4df79fa6fb
|
修复了上一次提交的错误。
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-03-09 12:11:54 +08:00 |
dmy@lab
|
f854799989
|
对于没有长度的头节点线路,设定一个阻抗最小值。
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-03-09 11:19:54 +08:00 |
dmy@lab
|
774a9339e8
|
解决头结点变化错误的问题。
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-03-09 10:31:33 +08:00 |
dmy@lab
|
d0b9071577
|
1.修复了单例模板的bug
2.正在加DG
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-30 21:34:31 +08:00 |
dmy@lab
|
cba2942574
|
把几节线路合并成一节
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-22 21:19:43 +08:00 |
dmy@lab
|
ca60dffe53
|
缩减元件还没成功
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-20 22:46:26 +08:00 |
dmy@lab
|
479bfc778a
|
1.修复子类初始化问题
2.加了id字段
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-20 21:24:33 +08:00 |
dmy@lab
|
da0a7f192e
|
把LineStru等类型声明放到单独的文件中。
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-20 20:59:47 +08:00 |
dmy@lab
|
5b9625f708
|
把网架信息输出到文件
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-20 15:56:30 +08:00 |
dmy@lab
|
8d5fcf9c95
|
1.把负荷文件路径加入CIMParser中。
2.把变压器也处理成双端支路。
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-20 13:19:28 +08:00 |
dmy@lab
|
214c17dd10
|
1.加了一个历遍所有子目录的类
2.加了读入所有匹配数据的功能。
Signed-off-by: dmy@lab <dmy@lab.lab>
|
2015-01-15 20:05:44 +08:00 |
facat@lab.com
|
9cb2f5a8f6
|
用CIMExporter分别处理读到的线路,开关,变压器等元件。
Signed-off-by: facat@lab.com <facat@lab.com>
|
2014-12-28 16:40:57 +08:00 |
facat@lab.com
|
4bc4f0ab3f
|
用类处理Breaker和Disconnector
Signed-off-by: facat@lab.com <facat@lab.com>
|
2014-12-27 21:50:51 +08:00 |
facat@lab.com
|
84d5330628
|
用类处理变压器阻抗数据。
Signed-off-by: facat@lab.com <facat@lab.com>
|
2014-12-27 21:45:46 +08:00 |
facat@lab.com
|
57dc9e9728
|
用类处理线路阻抗数据。
Signed-off-by: facat@lab.com <facat@lab.com>
|
2014-12-26 21:21:58 +08:00 |