dmy@lab
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46f890b77b
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修复了合并线路后没用重新计算阻抗的问题
Signed-off-by: dmy@lab <dmy@lab.lab>
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2015-03-09 16:26:47 +08:00 |
facat@lab.com
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84d5330628
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用类处理变压器阻抗数据。
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-27 21:45:46 +08:00 |
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facat@lab.com
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57dc9e9728
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用类处理线路阻抗数据。
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-26 21:21:58 +08:00 |
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facat@lab.com
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eadb1dedf3
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吧ACLineSegment的lineName换乘了namingDescription
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-12 16:41:36 +08:00 |
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facat@lab.com
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2e46068680
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加了Substation的类
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-11 19:57:55 +08:00 |
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facat@lab.com
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000f9b89fa
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1.注释掉一些不用的输出
2.删掉一些错误的注释
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-06 22:12:17 +08:00 |
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facat@lab.com
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69cd117f35
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1.修复了一些类的isTerminal没有被初始化的bug
2.修复了一些地方判断下一个Terminal的bug
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-06 21:48:07 +08:00 |
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facat@lab.com
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8bb30a0940
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不是用QStringRef，太容易出错。
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-11-24 22:01:30 +08:00 |
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facat@lab.com
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407fe62995
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把各种元件做出单独的类。
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-11-22 22:18:18 +08:00 |