dmy@lab
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46f890b77b
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修复了合并线路后没用重新计算阻抗的问题
Signed-off-by: dmy@lab <dmy@lab.lab>
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2015-03-09 16:26:47 +08:00 |
dmy@lab
|
f854799989
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对于没有长度的头节点线路,设定一个阻抗最小值。
Signed-off-by: dmy@lab <dmy@lab.lab>
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2015-03-09 11:19:54 +08:00 |
dmy@lab
|
479bfc778a
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1.修复子类初始化问题
2.加了id字段
Signed-off-by: dmy@lab <dmy@lab.lab>
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2015-01-20 21:24:33 +08:00 |
dmy@lab
|
5b9625f708
|
把网架信息输出到文件
Signed-off-by: dmy@lab <dmy@lab.lab>
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2015-01-20 15:56:30 +08:00 |
facat@lab.com
|
9cb2f5a8f6
|
用CIMExporter分别处理读到的线路,开关,变压器等元件。
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-28 16:40:57 +08:00 |
facat@lab.com
|
57dc9e9728
|
用类处理线路阻抗数据。
Signed-off-by: facat@lab.com <facat@lab.com>
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2014-12-26 21:21:58 +08:00 |